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products and specifications discussed herein ar e subject to change by aptina without notice. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor features pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 1 ?2006 aptina imaging corporation all rights reserved. 1/4.5-inch 1.6mp cmos digital image sensor MT9M002 for the latest MT9M002 data sheet, refer to aptinas web site: www.aptina.com features ? digitalclarity ? cmos imaging technology ? maximum frame rate (1284h x 812v/60 fps at 99 mhz) ? superior low-light performance ?low dark current ? global reset release (grr), which starts the exposure of all rows simultaneously ? simple two-wire serial interface ? programmable controls: gain , frame rate, frame size, exposure ? horizontal and vertical mirror image ? automatic black level calibration ? on-chip phase-locked loop (pll) oscillator ? bulb exposure mode for arbitrary exposure times ? snapshot mode to take frames on demand ? parallel data output ? electronic rolling shutter (ers), progressive scan ? programmable power-down mode (mode a or mode b) ? xenon and led flash support with fast exposure adaptation ? flexible support for mechanical shutter applications ? 720p high-definition digital video camcorder ? solid state (flash) pocket dvc ? digital still cameras ?pc cameras ? cellular phones table 1: key performance parameters ordering information table 2: available part numbers parameter value optical format 1/4.5-inch (4:3) active imager size 3.24mm(h) x 2.41mm(v) active pixels 1472h x 1096v pixel size 2.2 x 2.2 m color filter array rgb bayer pattern, mono shutter type global reset release (grr) (snapshot only), electronic rolling shutter (ers) maximum data rate/master clock 99 mp/s at 49.5 mhz (parallel) frame rate 1440h x 1080v programmable up to 30 fps 1280h x 720v programmable up to 60 fps adc resolution 12-bit, on-chip responsivity 1.4 v/lux-sec (550nm) 2.1 v/lux-sec (monochrome) dynamic range 70.1db snr max 38.1db supply voltage digital 1.7C1.9v i/o 2.6C3.1v pll 2.6C3.1v analog 2.6C3.1v power consumption 364.6mw at 2.8v (parallel) operating temperature C30c to +70c packaging 48-pin clcc or 48-pin ilcc part number description MT9M002c12stc 48-pin lead-free clcc/color/parallel/ 11.5 deg cra MT9M002i12stc 48-pin lead-free ilcc/color/parallel/ 0 deg cra
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 2 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 typical connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 pixel array structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 default readout order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 output data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 parallel pixel data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 output data timing (parallel pixel data interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 row timing details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 serial bus description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 bus idle state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 start bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 stop bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 slave address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 data bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 no-acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 two-wire serial interface sample write and read seq uences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 16-bit write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 signal chain and datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 analog gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 digital gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 analog black level calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 digital black level calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 pll-generated master clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 pll setup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 pll setup sample code for parallel mode after power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 maintaining a constant frame rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 synchronizing register writes to frame boundaries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 window size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 mirror mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 column mirror (color) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 row mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 image acquisition modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 electronic rolling shutter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 global reset release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 exposure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 strobe control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 3 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor table of contents timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 power-down sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 hard reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 signal state during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 standby and chip enable (power save mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 spectral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 cra characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 two-wire serial register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 dc electrical characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 4 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor list of figures list of figures figure 1: block diagram ? parallel output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: 48-pin clcc 10 x 10 package pinout diagram (top view) ? parallel interface. . . . . . . . . . . . . . . . . . . .9 figure 3: 48-pin ilcc 10 x 10 package pinout diagram (top view) ? parallel interface . . . . . . . . . . . . . . . . . . .11 figure 4: typical configuration ? parallel co nnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 5: pixel array description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 6: pixel color pattern detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 7: imaging a scene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 8: spatial illustration of image readout - parallel inte rface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 9: pixel data timing example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 10: row timing and frame_valid/line_valid signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 11: 1280x720/60 fps row timing details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 12: 1440x1080/30 fps mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 13: timing diagram showing a write to r0x09 with the valu e 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 14: timing diagram showing a read from r0x09; returned value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 15: signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 16: pll-generated master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 17: six pixels in normal and column mirror readout modes (color). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 18: six pixels in normal and column mirror readout modes (mono) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 19: six rows in normal and row mi rror readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 20: ers snapshot timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 21: grr snapshot timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 22: power supply power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 23: power supply power-down sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 24: typical color spectral characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 25: chief ray angle (cra) vs. image height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 26: two-wire serial bus timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 27: parallel i/o timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 28: 48-pin clcc package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 29: 48-pin ilcc package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 5 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor list of tables list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: signal descriptions for MT9M002 in clcc package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 4: signal descriptions for MT9M002 in ilcc package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 5: pixel type by column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 6: pixel type by row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 7: device addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 8: frequency parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 9: operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 10: strobe timepoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 11: power supply power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 12: power supply power-down timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 13: signal state during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 14: standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 15: two-wire serial bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 16: i/o timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 17: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 18: power consumption ? parallel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 19: absolute maximum values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 6 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor general description general description the aptina MT9M002 is a 1/4.5-inch format cmos active-pixel digital image sensor with a pixel array of 1472h x 1096v. the defaul t active imaging arra y size is 1440 x 1080. it incorporates sophisticated on-chip camera functions such as windowing, mirroring, and snapshot mode. it is programmable thro ugh a simple two-wire serial interface and has very low power consumption. the MT9M002 digital image sensor features digitalclarity?aptina?s breakthrough low- noise cmos imaging technology that achi eves near-ccd image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of cmos. functional overview the MT9M002 is a progressive-scan sensor th at generates a stream of pixel data at a constant frame rate. it uses an on-chip, phas e-locked loop (pll) to generate all internal clocks from a single ma ster input clock running between 8 and 16.5 mhz. user interaction with the sensor is through the two-wire serial bus, which communi- cates with the array control, analog signal chai n, and digital signal chain. the core of the sensor is a 1.6mp active-pixel array. the timing and control circuitry sequences through the rows of the array, resetting and then read ing each row in turn. in the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been read, the data from the colu mns is sequenced through an analog signal chain (providing offset correction and gain), and then through an adc. the output from the adc is a 12-bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which provid es further data path corrections and applies digital gain). the pixel data are output at a rate of up to 99 mp/s, in addition to frame and line synchronization signals in parallel mo de corresponding to a pixel clock rate of 99 mhz. figure 1 shows the block diagram of the sensor. figure 1: block diagram C parallel output d out [11:0] frame_val id line_valid pixclk sclk sdata reset_bar extclk serial interface array control pixel array 1600h x 1152v data path analog signal chain
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 7 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor functional overview the pixel array contains optically active and light-shielded (dark) pixels. the dark pixels are used to provide data for on-chip offset correction algorithms (black level control). the sensor contains a set of control and status registers that can be used to control many aspects of the sensor behavior including the frame size, exposure, and gain setting. these registers can be accessed through a two-wire serial interface. the output from the sensor (MT9M002i12stc)is a bayer pattern; alternate rows are a sequence of either green and red pixels or blue and green pixels. the offset and gain stages of the analog signal chain prov ide per-color control of the pixel data. a flash strobe output signal is provided to al low an external xenon or led light source to synchronize with the sensor exposure time an d to support the provision of an external mechanical shutter.
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 8 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor signal descriptions signal descriptions table 1 provides signal descriptions for the MT9M002 in a clcc package. table 1: signal descriptions for MT9M002 in clcc package pin numbers clcc name type description 26 sclk input serial clock. pull to v dd _io with a 1.5k resistor (depending on bus loading). 45 s addr 0 input serial address. pull to v dd _io with a 1.5k resistor (depending on bus loading). 28 s addr 1 input serial address. pull to v dd _io with a 1.5k resistor (depending on bus loading). 21 reset_bar input master reset signal, active low. 33 extclk input input clock signal 8C16.5 mhz. 5 trigger input snapshot trigger. used to trigger one frame of output in snapshot modes. 23, 25 test input enables manufacturing test modes. tie to digital gnd for functional operation. 27 s data i/o serial data. pull to v dd _io with a 1.5k resistor (depending on bus loading). 1 strobe output snapshot strobe. driven high when all pixels are exposing in snapshot modes. 4d out [0] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 48 d out [1] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 46 d out [2] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 20 d out [3] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 22 d out [4] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 24 d out [5] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 37 d out [6] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 35 d out [7] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 34 d out [8] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 38 d out [9] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 40 d out [10] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 41 d out [11] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 47 pixclk output pixel clock. used to qualify the line_valid, frame_valid, and d out (11:0). these outputs should be captured on the falling edge of this signal. 3 frame_valid output frame valid. qualified by pixclk. driven high during active pixels and horizontal blanking of each frame and low during vertical blanking. 2 line_valid output line valid output. qualified by pixclk. driven high with active pixels of each line and low during horizontal blanking periods. external pull down resistor to d gnd (typical 10kC100k) required for proper initialization sequence. 29, 44 v dd supply digital power 1.8v nominal. 10, 11 v aa _pix supply pixel array power 2.8v nominal.
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 9 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor signal descriptions figure 2: 48-pin clcc 10 x 10 package pinout diagram (top view) C parallel interface 7, 13, 18 v aa supply analog power 2.8v nominal. 32 v dd _pll supply pll power 2.8v nominal. 6, 19 v dd _io supply i/o power supply 2.8v nominal. 30, 31, 36,3 9, 42, 43 d gnd supply digital ground. 8, 12, 17 a gnd supply analog ground. 9, 14, 15, 1 6 nc C no connect. table 1: signal descriptions for MT9M002 in clcc package (continued) pin numbers clcc name type description 1 2 3 4 5 6 48474645 44 43 19 20 21 22 23 24 25 26 27 28 29 30 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32 31 v aa a gnd nc v aa _pix v aa _pix a gnd v aa nc nc nc a gnd v aa d gnd d out 11 d out 10 d gnd d out 9 d out 6 d gnd d out 7 d out 8 extclk v dd_ pll d gnd v dd_ io d out 3 et_bar d out 4 test d out 5 test s clk s data s addr 1 v dd d gnd v dd_ io trigger d out 0 frame_valid line_valid strobe d out 1 pixclk d out 2 s addr 0 v dd d gnd MT9M002 clcc parallel (top view)
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 10 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor signal descriptions table 2 provides signal descriptions for the MT9M002 in an ilcc package. table 2: signal descriptions for MT9M002 in ilcc package pin numbers ilcc name type description 26 sclk input serial clock. pull to v dd _io with a 1.5k resistor (depending on bus loading). 21 reset_bar input master reset signal, active low. 37 extclk input input clock signal 8C16.5 mhz. 5 trigger input snapshot trigger. used to trigger one frame of output in snapshot modes. 23, 25 test input enables manufacturing test modes. tie to digital gnd for functional operation. 27 s data i/o serial data. pull to v dd _io with a 1.5k resistor (depending on bus loading). 1 strobe output snapshot strobe. driven high when all pixels are exposing in snapshot modes. 4d out [0] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 48 d out [1] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 46 d out [2] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 20 d out [3] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 22 d out [4] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 24 d out [5] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 33 d out [6] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 32 d out [7] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 31 d out [8] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 40 d out [9] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 41 d out [10] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 42 d out [11] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 47 pixclk output pixel clock. used to qualify the line_valid, frame_valid, and d out (11:0). these outputs should be captured on the falling edge of this signal. 3 frame_valid output frame valid. qualified by pixclk. driven high during active pixels and horizontal blanking of each frame and low during vertical blanking. 2 line_valid output line valid output. qualified by pixclk. driven high with active pixels of each line and low during horizontal blanking periods. external pull down resistor to d gnd (typical 10kC100k) required for proper initialization sequence. 29, 44 v dd supply digital power 1.8v nominal. 10, 11 v aa _pix supply pixel array power 2.8v nominal. 7, 13, 18 v aa supply analog power 2.8v nominal. 36 v dd _pll supply pll power 2.8v nominal. 6, 19, 34, 3 9 v dd _io supply i/o power supply 2.8v nominal.
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 11 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor signal descriptions figure 3: 48-pin ilcc 10 x 10 package pinout diagram (top view) C parallel interface 28, 30, 35,3 8, 43, 45 d gnd supply digital ground. 8, 12, 17 a gnd supply analog ground. 9, 14, 15, 1 6 nc C no connect. table 2: signal descriptions for MT9M002 in ilcc package (continued) pin numbers ilcc name type description 1 2 3 4 5 6 4 84 7 4 64 5 44 43 19 20 21 22 23 24 25 26 27 28 29 30 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32 31 v aa a gnd nc v aa _pix v aa _pix a gnd v aa nc nc nc a gnd v aa d out 11 d out 10 d out 9 v dd_ io d gnd extclk v dd_ pll d gnd v dd_ io d out 6 d out 7 d out 8 v dd_ io d out 3 reset_bar d out 4 test d out 5 test sclk s data d gnd v dd d gnd v dd_ io trigger d out 0 frame_valid line_valid strobe d out 1 pixclk d out 2 d gnd v dd d gnd MT9M002 ilcc parallel (top view)
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 12 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor typical connections typical connections figure 4 shows typical connections for the MT9M002 sensor. for low-noise operation, the MT9M002 requires separate power supplies for analog and digital. incoming digital and analog ground conductors can be tied to gether next to the die. both power supply rails should be decoupled from ground using capacitors as close as possible to the die. the use of inductance filters is not recommended on the power supplies or output signals. the MT9M002 also supports different digital core (v dd /d gnd ) and i/o power (v dd _io/ d gnd ) power domains that can be at different voltages. pll requires a clean power source (v dd _pll). figure 4: typical configuration C parallel connection notes: 1. typical connection shows only one scenario out of multiple possible variations for this sensor. 2. all inputs must be configured with v dd _io. 3. v aa and v aa _pix must be tied together. d out [11:0] frame_valid pixclk strobe line_valid nc reset_bar sclk s data trigger extclk v dd _io v dd v dd _pll v aa _pix v aa a gnd 10k 1.5k v dd _io v dd v dd _pll v aa 1f test d gnd from controller master clock to image processor (open) 1.5k 10k
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 13 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor pixel array structure pixel array structure the MT9M002 pixel array consists of a 160 0-column by 1152-row matrix of pixels addressed by column and row. the address (column 0, row 0) represents the upper-right corner of the entire array, looking at the sensor, as shown in figure 5. the array consists of a 1440-column by 1080-ro w active region in the center representing the default output image resolution, surrounded by a boundary region (also active), surrounded by a border of dark pixels (see table 3 and table 4). the boundary region can be used to avoid edge effects when doing color processing, while the optically black column and rows can be used to monitor the black level. default readout order by convention, the sensor core pixel array is shown with pixel (0,0) in the top right corner (see figure 5). this reflects the actual layout of the array on the die. also, the first pixel data read out of the sensor in de fault condition is that of pixel (16,60). figure 5: pixel array description table 3: pixel type by column column pixel type 0C15 active boundary (16) 16C1455 active image (1440) 1456C1471 active boundary (16) 1472C1599 black (128) table 4: pixel type by row row pixel type 0C51 black (52) 53C59 active boundary (8) 60C1139 active image (1,080) 1140C1147 active boundary (8) 1148C1151 black (4) (1599, 1151) 0 black columns 4 black rows 52 black rows (0,0) 128 black columns active image 1440 x 1080 active pixels (16,60) (1455, 1139)
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 14 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor pixel array structure sensor pixels are output in a bayer pattern format consisting of four ?colors??greenr, greenb, red, and blue (gr, gb, r, b)?represe nting three filter colors. when no mirror modes are enabled, even-numbered rows contain alternate green1 and red pixels; odd- numbered rows contain alternate blue and green2 pixels. even-numbered columns contain greenr and blue pixels; odd-numbered columns contain red and greenb pixels. the greenr and greenb pixels have the same color filter, but they are treated as separate colors by the data path and analog signal chain. figure 6: pixel color pattern detail (top right corner) when the sensor is imaging, the active surface of the sensor faces the scene, as shown in figure 7. when the image is read out of the se nsor, it is read one row at a time, with the rows and columns sequenced, as shown in figure 6. figure 7: imaging a scene first clear pixel (0,52) black pixels column readout direction . . . . . . ... row readout direction r gb r gb r gb gr b gr b gr b r gb r gb r gb gr b gr b gr b r gb r gb r gb gr b gr b gr b lens pixel (0,0) row readout order column readout order scene sensor (rear view)
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 15 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor output data format output data format parallel pixel data interface MT9M002 image data is read out in a progre ssive scan. valid image data is surrounded by horizontal blanking and vertical blanking, as shown in figure 8. the amount of hori- zontal blanking and vertical blanking is pr ogrammable; line_valid is high during the shaded region of the figure. frame_valid ti ming is described in the next section. figure 8: spatial illustration of image readout - parallel interface p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image horizontal blanking vertical blanking vertical/horizontal blanking
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 16 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor output data timing (parallel pixel data interface) output data timing (parallel pixel data interface) the sensor core output data is synchronized with the pixclk output. when line_valid is high, one pixel data is output on the 12-bit d out output every pixclk period. by default, the internal pll is used and pixclk runs at the 2x master clock. the falling edge of pixclk appears at the center of the d out . this allows pixclk to be used as a clock to sample the data. by default, pixclk is not enabled, and its on or off is register controllable. when on, pixclk is continuously enabled, even during the blanking period. the MT9M002 can be programmed to delay the pixclk edge relative to the d out transitions. this can be achieved by programming the corresponding register bits. figure 9: pixel data timing example figure 10: row timing and frame_valid/line_valid signals the sensor timing is shown in terms of pixel clock and master clock cycles (figure 9 and figure 10). p 0 [11:0] p 1 [11:0] p 2 [11:0] p 3 [11:0] p 4 [11:0] p 5 p n-2 p n-1 [11:0] p n [11:0] valid image data blanking blanking l ine_valid pixclk d out(11:0) frame_valid line_valid n umber of master clocks p a q aqap
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 17 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor output data timing (parallel pixel data interface) row timing details this section discusses row timing for 1440 x 1080 30fps and 1280 x 720 60 fps modes. in figure 11 and figure 12, h-bl is horizontal blan king, ob is optically black columns, h is one row, and v-bl is vertical blanking. the pixel clock is two times master clock (pclk = 99 mhz, mclk = 49.5 mhz). each pclk output s one active pixel or one black pixel. h-bl setting value uses mclk as a unit (one horizontal blank needs two pclks). figure 11: 1280x720/60 fps row timing details ? mclk = 49.5 mhz h = h-bl + active cols/2+ ob/2 h = 404 mclks + 656 mclks + 40 mclks = 1100 mclks = 22.22 s ? v = 14h + 736h = 750h t frame = h x v = 1100 x750 = 825000 mclks = 825000 mclks/49.5 mhz = 16.66ms ? frame rate = 1/ t frame = 1/16.66ms = 60 fps ? active readout window is 1312 (1280+32 boundary) columns x 736 (720+16 boundary) rows figure 12: 1440x1080/30 fps mode ? mclk = 49.5 mhz ? h = h-bl + active cols/2 + ob/2 = 424 clks + 736 mclks + 40 mclks = 1200 mclks = 24.24 s ? v = 279h + 1096h = 1375h ? t frame = h x v = 1200 x 1375 = 1650000 mclks = 1650000 mclks/49.5 mhz = 33.33ms ? frame rate = 1/ t frame = 1/33.33ms = 30 fps ? active readout window is 1472 (1440+32 boundary) columns x 1096 (1080+16 boundary) rows 1h 404mclk 656mclk 40mclk h-bl active 1312 cols 80 ob 14h 736h v-bl active rows 1h 424mclk 736mclk 40mclk h-bl active 1472 cols 80 ob 279h 1096h v-bl active rows
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 18 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor serial bus description serial bus description registers are written to and read from the MT9M002 through the two-wire serial inter- face bus. the MT9M002 is a serial interface slave and is controlled by the serial clock (sclk), which is driven by the serial interface master. data is transferred into and out of the MT9M002 through the serial data (s data ) line. the s data line is pulled up to v dd _io off-chip by a 1.5k resistor. either the slave or master device can pull the s data line low?the serial interface protocol determines which device is allowed to pull the s data line down at any given time. protocol the two-wire serial defines several diffe rent transmission codes, as follows: ?a start bit ? the slave device 8-bit address ? an (a no) acknowledge bit ? an 8-bit message ?a stop bit sequence a typical read or write sequence begins by th e master sending a start bit. after the start bit, the master sends the slave device's 8-bi t address. the last bit of the address deter- mines if the request is a read or a write, where a ?0? indicates a write and a ?1? indi- cates a read. the slave device acknowledges its address by sending an acknowledge bit back to the master. if the request was a write, the master then transfers the 8-bit register address to which a write should take place. the slave sends an acknowledge bit to indicate that the register address has been received. the master then transfers the data 8 bits at a time, with the slave sending an acknowledge bit after each 8 bits. the MT9M002 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. after 16 bits are transferred, the register ad dress is automatically incremented, so that the next 16 bits are written to the next regi ster address. the master stops writing by sending a start or stop bit. a typical read sequence is executed as foll ows. first the master sends the write-mode slave address and 8-bit register address, just as in the write request. the master then sends a start bit and the read-mode slave address. the master then clocks out the register data 8 bits at a time. the master sends an acknowledge bit after each 8-bit transfer. the register address is automatically incremented after every 16 bits is trans- ferred. the data transfer is stopped when the master sends a no-acknowledge bit. bus idle state the bus is idle when both the data and cloc k lines are high. control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. only the master can generate the start and stop bits. start bit the start bit is defined as a high-to-low transi tion of the data line while the clock line is high.
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 19 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor serial bus description stop bit the stop bit is defined as a low-to-high transi tion of the data line while the clock line is high. slave address for the ilcc package, the 8-bit address of the tw o-wire serial interfac e device consists of 7 bits of address and 1 bit of direction. a ?0? in the lsb (least significant bit) of the address indicates write mode (0xb8), and a ?1? indicates read mode (0xb9). the two-wire serial interface device addresse s consists of 7 bits. for the MT9M002 ilcc package sensor (parallel interface) th e device address is fixed at [1011100]. for the clcc package, the MT9M002 allows for multiple device addresses in master/ slave mode as shown in table 5. the 2 lsbs of the device address are defined by s addr 0 and s addr 1 input port values. data bit transfer one data bit is transferred during each clock pulse. the serial interface clock pulse is provided by the master. the data must be stab le during the high period of the two-wire serial interface clock?it can only change wh en the serial clock is low. data is trans- ferred 8 bits at a time, foll owed by an acknowledge bit. acknowledge bit the master generates the acknowledge clock pu lse. the transmitter (which is the master when writing, or the slave when reading) re leases the data line, and the receiver indi- cates an acknowledge bit by pulling the data line low during the acknowledge clock pulse. no-acknowledge bit the no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. a no-acknowledge bit is used to terminate a read sequence. table 5: device addresses s addr 1 s addr 0 device address 0 0 0xb8 0 1 0xba 1 0 0xbc 1 1 0xbe
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 20 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor two-wire serial interface sample write and read sequences two-wire serial interface sample write and read sequences 16-bit write sequence a typical write sequence for writing 16 bits to a register is shown in figure 13. a start bit given by the master, followed by the write address, starts the sequence. the image sensor then sends an acknowledge bit and expects the register address to come first, followed by the 16-bit data. after each 8-bit transfer, the image sensor sends an acknowledge bit. all 16 bits must be written before the register is updated. after 16 bits are transferred, the register address is automatically incremented so that the next 16 bits are written to the next register. the master stops writ ing by sending a start or stop bit. figure 13: timing diagram showing a write to r0x09 with the value 0x0284 16-bit read sequence a typical read sequence is shown in figure 14. first the master has to write the register address, as in a write sequence. then a start bit and the read address specify that a read is about to happen from the register. the master then clocks out the register data 8 bits at a time. the master sends an acknowledge bit after each 8-bit transfer. the register address is incremented after every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. figure 14: timing diagram showing a read from r0x09; returned value 0x0284 sclk s data start ack 0xb8 addr ack ack ack stop r0x09 1000 0100 0000 0010 sclk s data start ack 0xb8 addr 0xb9 addr 0000 0010 r0x09 ack ack ack stop 1000 0100 nack start
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 21 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor signal chain and datapath signal chain and datapath the signal chain and datapath are shown in figure 15. each color is processed indepen- dently, including separate gain and offset settings. voltages sampled from the pixel array are first passed through an analog gain stag e, which can produce gain factors between 1 and 7.875. an analog offset is then applied, and the signal is sent through a 12-bit analog-to-digital converter. in the digital space, a digital gain factor of between 1 and 16 is applied, and then a digital offset of betw een ?2048 and 2047 is added. the resulting 12- bit pixel value is then output on the d out [11:0] ports. the analog offset applied is determined au tomatically by the black level calibration algorithm, which attempts to shift the output of the analog signal chain so that black is maintained. the digital offset is a fine-tuning of the analog offset. figure 15: signal path gains the MT9M002 supports two types of gain: anal og gain and digital gain. combined, gains of between 1 and 126 are possible. it is reco mmended that analog gain should be maxi- mized before applying digital gain. the sensor provides per-color gain control as well as the option of global gain control. per-color and global gain control can be used interchangeably. a write to a global gain register is aliased as a write of the same data to the four associated color-dependent gain registers. the combined gain for a color c is given by: g c = ag c x dg c (eq 1) analog gain the analog gain is specified independently for each color channel. there are two components, the gain and the multiplier. the gain is specified by green1_analog_gain, red_analog_gain, blue_analog_gain, and gr een2_analog_gain. the analog multiplier is specified by green1_analog_multiplier, red_analog_multiplier, blue_analog_multiplier, and green2_analog_m ultiplier. these combine to form the analog gain for a given color c, as shown in this equation: ag c = (1 + c_analog_multiplier) (c_analog_gain / 16) (eq 2) the gain component can range from 0 to 7.875 in steps 0.0625 for <4 gain, and 0.125 for >4 gain, and the multiplier component can be ei ther 0 or 1 (resulting in a multiplier of 1 or 2). however, it is best to keep the gain component between 1 and 4 for the best noise performance, and use the multiplier for gains between 4 and 7.825.
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 22 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor signal chain and datapath digital gain the digital gain is specified independently for each color channel in steps of 0.125. it is controlled by the register fields gr een1_digital_gain, red_digital_gain, blue_digital_gain, and green2_digital_gain. the digital gain for a color c is given by: dg c = 1 + (c_digital_gain / 8) (eq 3) offset the MT9M002 sensor can apply an offset or shift to the image data in several ways. an analog offset can be applied on a color-wise basis to the pixel voltage as it enters the adc. this makes it possible to adjust for offset introduced in the pixel sampling and gain stages to be removed, centering the resu lting voltage swing in the adc's range. this offset can be automatically determined by the sensor using the automatic black level calibration (blc) circuit, or it can be set manual ly by the user. it is a fairly coarse adjust- ment, with adjustment step sizes of four to eight lsbs. digital offset is also added on a color-wise and line-wise basis to fine-tune the black level of the output image. this offset is based on an average black level taken from each row's dark columns, and is automatically determined by the digital row-wise black level cali- bration (rblc) circuit. if the rblc circuit is not used, a user-defined offset can be applied instead. this offset has a resolution of 1 lsb. a digital offset is added on a color-wise basis to account for channel offsets that can be introduced due to "even" and "odd" pixels of the same color going through a slightly different adc chain. this offset is automatically determined based on dark row data, but it can also be manually set. analog black level calibration the MT9M002 black level calibration circuitry provides a feedback control system since adjustments to the analog offset are imprecise by nature. the goal is that within the dark row region of any supported output image si ze, the offset should have been adjusted such that the average black level falls within the specified target thresholds. the analog offsets normally need a major ad justment only when leaving the reset state or when there has been a change to a color' s analog gain. factors like shutter width and temperature have lower-order impact, and generally only require a minor adjustment to the analog offsets. the MT9M002 has various calibration modes to keep the system stable while still supporting the need for rapid offset adjustments when necessary. digital black level calibration digital black level calibration is the final calc ulation applied to pixel data before it is output. it provides a precise black level to complement the coarser-grained analog black level calibration, and also corrects for black level shift introduced by digital gain. this correction applies to the active columns for all rows, including dark rows.
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 23 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor features features pll-generated master clock the pll can generate a pixclk clock signal whose frequency is up to 99 mhz (input clock from 8?16.5 mhz). the pll-generated clock can be controlled by programming the appropriate register. it is possible to bypa ss the pll and use extclk as master clock. by default, the pll is powered up. the pll contains a prescaler to divide th e input clock applied on extclk, a vco to multiply the prescaler output, and pll output divider stage to generate the output clock. the clocking structure is shown in figure 16. pll control can be programmed to generate desired pi xel clock frequency. figure 16: pll-generated master clock note: the pll control registers must be programm ed while the sensor is in the software standby state. the effect of programming the pll divisors while the sensor is in the streaming state is undefined. extclk pll output clock pll_n_divider +1 pre pll div (pfd) pll input clock pll multiplier (vco) pll output div pll_out_divider(6) pll_m_factor sysclk (pixclk) n m
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 24 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor features pll setup sequence to use the pll: 1. power up the MT9M002; ensure that f extclk is between 8 and 16.5 mhz. 2. put the MT9M002 into master mode. 3. set the pll out divider to 7 (refer to ?pll setup sample code for parallel mode after power-up? below). note: the power-up default pll out divider setting is 6. 4. set pll_m_factor and pll_n_divider based on the desired input ( f extclk = 13.5 mhz) and output ( f pixclk = 99 mhz) frequencies. using this formula: f pixclk = f vco / 7 (eq 4) where f vco = ( f extclk x m) / n m = pll_m_factor, n = (pll_n_divider + 1) 5. wait 1ms to ensure that the vco has locked. 6. select the pll as the clock source. 7. enable the parallel data output. pll setup sample code for parallel mode after power-up (with input clock frequency 13.5 mhz) 1. set r0x1e = 0x8006 // master mode 2. set r0x9f = 0x0070 // set-up for changing to 14-bit mode. 3. set r0x9e = 0x101e // set 14-bit mode, select 7 divider, parallel mode. 4. set r0x11 = 0x9a02 // assuming an input extclk of 13.5 mhz, generates an output pixclk of 99 mhz. 5. delay = 1ms // ensures vco has locked. 6. set r0x10 = 0x0053 // select pll as clock source. 7. set r0x9f = 0x3070 // parallel data out. note: the registers r0x9e and r0x9f need to be set to different values for serial operation. the code example shows the values for parall el operation. for the serial operation: r0x9f = 0xc070, r0x9e = 0x001e. table 6: frequency parameters parameter equation min max unit pll_n_divider C 0 63 pll_m_factor C 16 255 f extclk C 8 16.5 mhz f pfd f extclk /(pll_n_divider+1) 2 24 mhz f vco f extclk * pll_m_factor/(pll_n_divider+1) 320 693 mhz
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 25 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor features maintaining a constant frame rate maintaining a constant frame rate while contin uing to have the ability to adjust certain parameters is often desired. this is not alwa ys possible, however, since register updates are synchronized to the read pointer, and the shutter pointer for a frame is usually active during the readout of the previous frame. therefore, any register changes that could affect the row time or the set of rows sample d causes the shutter pointer to start over at the beginning of the next frame. by default, the following register fields caus e a "bubble" in the output rate (the vertical blank increases for one frame) if they are written in continuous mode, even if the new value would not change the resulting frame rate: ? row_start ?row_size ?column_size ?horizontal_blank ?vertical_blank ? shutter_delay ? mirror_row the size of this bubble is (sw t row), calculating the row time according to the new settings. the shutter_width_lower and shutter_widt h_upper fields may be written without causing a bubble in the output rate unde r certain circumstances. since the shutter sequence for the next frame often is active du ring the output of the current frame, this would not be possible without special provisio ns in the hardware. writes to these regis- ters take effect two frames after the frame they are written, which allows the shutter width to increase without interrupting the ou tput or producing a corrupt frame (as long as the change in shutter width does not affect the frame time). synchronizing register writ es to frame boundaries changes to most register fields that affect th e size or brightness of an image take effect on the frame after the one during which they are written. these fields are noted as ?synchronized to frame boundaries? in table 6 on page 24. to ensure that a register update takes effect on the next frame, the write operation must be completed after the leading edge of fv and before the trailing edge of fv. as a special case, in snapshot modes (see belo w), register writes that occur after fv but before the next trigger will take effect imme diately on the next frame, as if there had been a restart. however, if the trigger for the next frame in ers snapshot mode occurs during fv, register writes take effect as with continuous mode. additional control over the timing of register updates can be achieved by using synchronize_changes. if this bit is set, writes to certain register fields that affect the brightness of the output image do not take effect immediately. instead, the new value is remembered internally. when synchronize_ch anges is cleared, all the updates simulta- neously take effect on the next frame (as if they had all been written the instant synchronize_changes was cleared). register fields affected by this bit are identified in table 2: core registers ? register description on page 10 of the register reference. fields not identified as being frame-synchronized or affected by synchronize_changes are updated immediately after the register writ e is completed. the effect of these regis- ters on the next frame can be difficult to predict if they affect the shutter pointer.
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 26 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor features restart to restart the MT9M002 at any time during the operation of the sensor, write a ?1? to the restart register (r0x0b[0] = 1). this has two e ffects: first, the current frame is interrupted immediately. second, any writes to frame-synchronized registers and the shutter width registers take effect immediately, and a new frame starts (in continuous mode). register updates being held by synchronize_changes do not take effect until that bit is cleared. the current row and one following row complete before the new frame is started, so the time between issuing the rest art and the beginning of the next frame can vary by about t row. if pause_restart is set, rather than immedi ately beginning the next frame after a restart in continuous mode, the sensor pauses at the beginning of the next frame until pause_restart is cleared. this can be used to achieve a deterministic time period from clearing the pause_restart bit to the beginni ng of the first frame, meaning that the controller does not need to be tightly synchronized to lv or fv. note: when pause_restart is cleared, be sure to le ave restart set to ?1? for proper operation. the restart bit will be cleared automatically by the device. window size the output image window of the pixel array (the fov) is programmable and defined by four register fields. column_start and row_start define the x and y coordinates of the upper left corner of the fov. column_size defines the width of the fov, and row_size defines the height of the fov in array pixels. the column_start and row_start fields must be set to an even number. the column_size and row_size fields must be set to odd numbers (resulting in an even size for the fov). the row_start register should be set no lower than 12 if either manual_blc is cleared or show_dark_rows is set. the width of the output image, w, is column_size + 1 and height, h, is row_size + 1 . in default, a full resolution image size of 1440 x 1080 in output.
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 27 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor features readout modes the MT9M002 sensor supports mirror readout mode. images can be flipped in the vertical and/or mirrored in the horizontal directions. mirror mode by default, active pixels in an image are output in row-major order (an entire row is output before the next row is begun), from lowest row/column number to highest. mirror mode allows the output order of the rows and columns to be reversed. this only affects pixels in the active region of the image, not pixels read out as dark rows or dark columns. when the readout direction is reversed, the color order is reversed as well (for example, red, green, red, and so on instead of green, red, green, and so on), thus causing the bayer order of the output image to change. column mirror (color) the readout order of the columns are reversed, as shown in figure 17. figure 17: six pixels in normal and column mirror readout modes (color) row mirror the readout order of the rows are reversed, as shown in figure 18. figure 18: six pixels in normal and column mirror readout modes (mono) figure 19: six rows in normal and row mirror readout modes d out [11:0] line_valid normal readout g0 (11:0) r0 (11:0) g1 (11:0) r1 (11:0) g2 (11:0) r2 (11:0) d out [11:0] reversed readout g2 (11:0) r1 (11:0) g1 (11:0) r0 (11:0) g0 (11:0) r2 (11:0) d out [11:0] line_valid normal readout col0 (11:0) col1 (11:0) col2 (11:0) col3 (11:0) col4 (11:0) col5 (11:0) d out [11:0] reversed readout col4 (11:0) col5 (11:0) col3 (11:0) col2 (11:0) col1 (11:0) col0 (11:0) d out [11:0] line_valid normal readout row0 row1 row2 row3 row4 row5 d out [11:0] reverse readout row0 row1 row2 row3 row4 row5
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 28 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor features image acquisition modes the MT9M002 supports two image acquisition modes (shutter types), electronic rolling shutter (ers), and global reset release (grr). electronic rolling shutter the ers modes take pictures by scanning the rows of the sensor. on the first scan, each row is released from reset, starting the exposure. on the second scan, the row is sampled, processed, and returned to the reset state. the exposure for any row is therefore the time between the first and second scans. each ro w is exposed for the same duration, but at slightly different point in time, which can cause a shear in moving subjects. whenever the mode is changed to an ers mode (even from another ers mode), and before the first frame following reset, there is an anti-blooming sequence where all rows are placed in reset. this sequence must complete before continuous readout begins. this delay is: t allreset = 16 1096 t aclk (where t aclk is 2 * t pixclk) (eq 5) global reset release the grr modes attempt to address the shearing effect by starting exposures of all rows at the same time. instead of the first scan used in ers mode, the reset to each row is released simultaneously. the second scan oc curs as normal, so th e exposure time for each row would different. typically, an external mechanical shutter would be used to stop the exposure of all rows simultaneously. in grr modes, there is a startup overhead be fore each frame as all rows are initially placed in the reset state ( t allreset). unlike ers mode, this delay always occurs before each frame. however, it occurs as soon as possible after the preceding frame, so typically the time from trigger to the start of exposure does not include this delay. to ensure that this is the case, the first trigger must occur no sooner than t allreset after the previous frame is read out. exposure the nominal exposure time, t exp, is the effective shutter time in ers modes, and is defined by the shutter width (sw), r8, r9 an d the shutter overhead (so), which includes the effect of shutter_delay. exposure time for other modes is defined relative to this time. increasing shutter_delay (sd), r12 decreases the exposure time. exposure times are typically specified in units of row time, increasing or decreasing the shutter width (sw) register value will make exposure times increase or decrease in units of row time. it is also possible to fine-tune exposures in units of t aclks (where t aclk = 2 * t pixclk) by adjusting the shutter_delay (sd) register. this is expressed in the formula: t exp = sw t row ? so 2 t pixclk (eq 6) if the sd register value does not change, the (so x 2 x t pixclk) in above formula is a constant offset of exposure time. most ap plications do not need to change the sd register, except when fine-tuning the exposure time in units of t aclk. under normal conditions in ers modes, every pixel should end up with the same exposure time. in global shutter release modes, the exposure times of individual pixels can vary.
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 29 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor features in global shutter release modes (described later), exposure time starts simultaneously for all rows, but still ends as defined above. in a real system, the exposure would be stopped by a mechanical shutter, which would effectively stop the exposure to all rows simultaneously. since this specification does not consider the effect of an external shutter, each output row's exposure time will differ by t row from the previous row. global shutter modes also introduce a constant added to the shutter time for each row, since the exposure starts during the global shutter sequence, and not during any row's shutter sequence. in bulb_exposure modes (also detailed later), the exposure time is determined by the width of the trigger pulse rather than the sh utter width registers. in ers bulb mode, it will still be a multiple of row times, and the shutter overhead equation still applies. in grr bulb mode, the exposure time is granular to aclks, and shutter overhead (and thus shutter_delay) have no effect. operating modes in the default operating mode, the MT9M002 continuously samples and outputs frames. it can be put in snapshot or triggered mode by setting snapshot, which means that it samples and outputs a frame only when triggered. to leave snapshot mode, it is neces- sary to first clear snapshot then issue a restart. when in snapshot mode, the sensor can use the ers or the grr. the exposure can be controlled as normal, with the shutter_width_lower and shutter_width_upper regis- ters, or it can be controlled using the external trigger signal. the various operating modes are summarized in table 7. notes: 1. in ers bulb mode, sw must be greater than 4 (use trigger wider than t row*4). all operating modes share a common set of operations: 8. wait for the first trigger, then start the exposure. 9. wait for the second trigger, then start the readout. the first trigger is by default automatic, prod ucing continuous images. if snapshot is set, the first trigger can either be a low level on the trigger pin or writing a ?1? to the trigger register field. if invert_trigger is set, the first trigger is a high level on trigger pin (or a ?1? written to trigger register field) . since trigger is level-sensitive, multiple frames can be output (with a frame rate of t frame) by holding trigger pin at the trig- gering level. table 7: operating modes mode settings description ers continuous default frames are output continuously at the frame rate defined by t frame. ers is used, and the exposure time is electronically controlled to be t exp. ers snapshot snapshot = 1 frames are output one at a time, with each frame initiated by a trigger. ers is used, and the exposure time is electronically controlled to be t exp. ers bulb snapshot = 1; bulb_exposure = 1 frames are output one at a time, with each frame's exposure initiated by a trigger. ers is used. end of exposure and readout are initiated by a second trigger. grr snapshot snapshot = 1; global_reset = 1 frames are output one at a time, with each frame initiated by a trigger. grr is used. readout is electronically triggered based on sw. grr bulb snapshot = 1; bulb_exposure = 1; global_reset = 1 frames are output one at a time, with each frame initiated by a trigger. grr is used. readout is initiated by a second trigger.
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 30 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor features the second trigger is also normally automatic, and generally occurs sw row times after the exposure is started. if bulb_exposure is set, the second trigger can either be a high level on trigger or a write to restart. if invert_trigger is set, the second trigger is a low level on trigger (or a restart). in bulb modes, the minimum possible exposure time depends on the mechanical shutter used. after one frame has been output, the chip will reset back to step 1 above, eventually waiting for the first trigger again. the next trigger may be issued after ((vb - 8) x t row ) in ers modes or t allrest in grr modes. the choice of shutter type is made by global_reset. if it is set, the grr shutter is used; otherwise, ers is used. the two shutters are described in ?electronic rolling shutter? on page 28 and ?global reset release? on page 28. the default ers continuous mode is shown in figure 5 on page 13. figure 20 shows default signal timing for ers snapshot mode s, while figure 21 on page 31 shows default signal timing for grr snapshot modes. figure 20: ers snapshot timing trigger strobe frame_valid line_valid d out trigger strobe frame_valid line_valid d out (a) ers snapshot (b) ers bulb tt1 tse tsw tt2 (h + vb) x t row (h + vb) x t row 8 x t row t row t row 8 x t row t row 8 x t row t row sw x t row 8 x t row first row exposure second row exposure first row exposure second row exposure sw x t row tt1 tsw tt2 tse
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 31 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor features figure 21: grr snapshot timing strobe control to support synchronization of the exposure with external events such as a flash or mechanical shutter, the MT9M002 produces a st robe output. by default, this signal is asserted for approximately the time that all rows are simultaneously exposing, minus the vertical blank time, as shown in figure 20 on page 30 and figure 21. also indicated in these figures are the leading and trailing edges of strobe, which an be configured to occur at one of several timepoints. the lead ing edge of strobe occurs at strobe_start, and the trailing edge at strobe_end, whic h are set to codes described in table 8. if strobe_start and strobe_end are set to the same timepoint, the strobe is a t row wide pulse starting at the strobe_start ti mepoint. if the settings are such that the strobe would occur after the trailing edge of fv, the strobe may be only t aclk wide; however, since there is no concept of a row at that time. the sense of the strobe signal can be inverted by setting invert_strobe (r0x1e [5] = 1). to use strobe as a flash in snap- shot modes or with mechanical shutter, set the strobe_enable register bit field (r0x1e[4] = 1). table 8: strobe timepoints symbol timepoint code tt1 trigger 1 (start of shutter scan) C tse start of exposure (all rows simultaneously exposing) offset by vb 1 tsw end of shutter width (expiration of the internal shutter width counter) 2 tt2 trigger 2 (start of readout scan) 3 trigger strobe frame_valid line_valid d out trigger strobe frame_valid line_valid d out (a) grr snapshot (b) grr bulb tse tsw tt2 tsw tse tt2 vb x t row + 2000 x t aclk t row 8 x t row t row 8 x t row first row exposure first row exposure vb x t row + 2000 x t aclk second row exposure second row exposure sw x t row + 2000 x t aclk sw x t row + 2000 x t aclk tt1 tt1
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 32 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor timing specifications timing specifications power-up sequence use the following sequence when powering up the MT9M002: 1. ensure reset_bar is asserted (driven low). 2. bring up all the power supplies at the same time. if both the analog and the digital supplies cannot be brought up simultaneously, ensure the digital supply comes up first. ensure that all power rails reach minimum voltages. 3. de-assert reset_bar (driven high). 4. after reset, the sensor must be activated to gene rate output image data. to active it, the user must load a set of initial file settings. the simplest set of power on initialial- izations setting is: reg = 0, 0x1e, 0xc006 // set parallel mode reg = 0, 0x9f, 0x3070 // parallel data and clock out reg = 0, 0x9e, 0x111e // fv_lv timing adjustment reg = 0, 0x0b, 0x0001 // restart delay = 100 reg = 0, 0x0b, 0x0000 //restart figure 1: power supply power-up sequence notes: 1. the line_valid signal must be connected to an external pull-down resistor (typically from 10kC100k ). 2. the dotted lines are drawn in reference to the minimum voltage of the power supply or minimum vih for reset_bar. please refer table 3 on page 41 for dc electrical specifications. 3. after all power rails reach their minimum voltage value, reset_bar should stay at low at least one mil- lisecond. at least one stable extclk input is required before reset_bar is released. v dd _ io v dd v dd _ pll v aa , v aa _pix extclk reset_bar 2.8v 1.8v 2.8v 2.8v power up t 3 t 4 t2 t 1
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 33 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor timing specifications power-down sequence follow this sequence to power down the sensor. see figure 2 for detailed timing. 1. assert reset_bar (driven low). 2. remove all power supplies simultaneously or at least within th e timing parameters specified in table 2. figure 2: power supply power-down sequence table 1: power supply power-up timing parameter symbol min typ max units v dd _io to v dd t 10C500 ms v dd to v dd _pll t 20C500 v dd _pll to v aa , v aa _pix t 30C500 reset activation t 41CC table 2: power supply power-down timing parameter symbol min typ max units v aa , v aa _pix to v dd _pll t 10C500 ms v dd _pll to v dd t 20C500 v dd to v dd _io t 30C500 reset activation t 41CC v aa, v aa _pix v dd _ pll v dd v dd_ io extclk reset_bar 2.8v 2.8v 1.8v 2.8v power down t 3 t 4 t 2 t 1
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 34 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor timing specifications reset two types of reset are available: ? a hard reset is issued by toggling reset_bar. ? a soft reset is issued by writing commands through the serial interface. hard reset assert (low) reset_bar and apply at least on e extclk pulse. all registers return to the factory defaults. when the signal is de-asserted (high), the chip resumes normal operation. soft reset a soft reset to the sensor has the same affect as the hard reset and can be activated by setting the register field to ?1?: r0x0d[0] = 1. all registers except the following will be reset: ?chip_enable ? synchronize_changes ?reset ? pll_m_factor ? pll_n_divider when the field is returned to "0," the chip resumes normal operation. signal state during reset table 3 shows the state of the signal in terface during reset (when reset_bar is asserted) and during standby (after exit from reset and before any registers within the sensor have been changed from their default power-up values). standby and chip enable (power save mode) the MT9M002 can be put in a low-power standby state from streaming state by programming r0x07[1]. two standby mode s (stby_a and stby_b ) are selectable through r0x10[13:12]. conditions are shown in table 4. when the sensor is put in standby, all internal clocks are gated, and anal og circuitry is put in a state that it draws minimal power. table 3: signal state during reset signal name signal type reset signal state sclk input input reset_bar input input extclk input input trigger input input test input input s data i/o input strobe output tri-state d out [11:0] output output pixclk output high frame_valid input input line_valid input input
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 35 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor timing specifications the two-wire serial interface remains minima lly active so that the chip_enable bit can subsequently be cleared. reads cannot be performed and only the chip_enable register is writable. if the sensor was in continuous mode when put in standby, it resumes from where it was when standby was deactivated. for maximum power savings in standby mode, extclk should not be toggling. when standby mode is entered, the pll is disabled automati- cally or powered down. it must be manually re-enabled when leaving standby as needed. note: stby_b is for master mode in the system, which keeps to output sync (fv / lv) sig- nals. stby_a is for both modes. to enter standby stby_a: 1. set r0x027[7] = 1 2. set r0x094[0] = 1 3. set r0x00b = 0x0003 4. set r0x007[1] = 0 to enter standby stby_b: set r0x00a[12:13] = 1 to leave standby stby_a: 1. set r0x027[7] = 0 2. set r0x094[0] = 0 3. set r0x00b = 0x0000 4. set r0x007[1] = 1 5. set r0x010[1] = 0 6. set r0x010[1] = 1 to leave standby stby_b: set r0x00a[12:13] = 0 note: the execution of standby will take place after the completion of the current line by default. table 4: standby modes circuit type stby_a stby_b analog core disable disable digital data pass array control disable enable digital ac disable enable digital clk gen (gated clock ctrl) enable (master clock bypass) enable pll disable enable
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 36 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor spectral characteristics spectral characteristics figure 1: typical color spectral characteristics quantum efficiency vs. wavelength 0 5 10 15 20 25 30 35 40 45 50 350 450 550 650 750 wavelength (nm) quantum efficiency ( % )
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 37 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor cra characteristics cra characteristics figure 2: chief ray angle (cra) vs. image height cra vs. image height plot image height cra (%) (mm) (deg) 000 5 0.099 0.66 10 0.198 1.32 15 0.297 1.98 20 0.396 2.66 25 0.495 3.33 30 0.594 4.01 35 0.693 4.68 40 0.792 5.36 45 0.891 6.04 50 0.990 6.71 55 1.089 7.36 60 1.188 7.98 65 1.287 8.58 70 1.386 9.13 75 1.485 9.63 80 1.584 10.09 85 1.683 10.51 90 1.782 10.90 95 1.881 11.24 100 1.980 11.53 0 2 4 6 8 10 12 14 0 10 20 30 40 50 60 70 80 90 100 110 image height (%) cra (deg)
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 38 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor electrical specifications electrical specifications two-wire serial register interface the electrical characteristics of the two- wire serial register interface (sclk, s data ) are shown in figure 3 and table 1. figure 3: two-wire serial bus timing parameters note: read sequence: for an 8-bit read, read waveforms start after write command and register address are issued. table 1: two-wire serial bus characteristics symbol parameter condition min typ max unit f sclk serial interface input clock frequency C C C 400 khz t sclk serial input clock period C 2.5 C C ?s sclk duty cycle C 40 50 60 % tr_sclk sclk rise time C 300 ns tf_sclk sclk fall time C 300 ns tr_sdat s data rise time C 300 ns tf_sdat s data fall time C 300 ns t srth start hold time write/read 600 ns t sdh s data hold write ns t sds s data setup write ns t shaw s data hold to ack write ns t ahsw ack hold to s data write ns t stps stop setup time write/read ns t stph stop hold time write/read ns t shar s data hold to ack read ns t ahsr ack hold to s data read ns t sdhr s data hold read ns t sdsr s data setup read ns s data sclk write start ack stop s data sclk read start ack tr_clk tf_clk 90% 10% tr_sdat tf_sdat 90% 10% t sdh t sds t shaw t ahsw t stps t stph register address bit 7 write address bit 0 register value bit 0 register value bit 7 read address bit 0 register value bit 0 write address bit 7 read address bit 7 t shar t sdsr t sdhr t ahsr t srth t sclk
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 39 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor electrical specifications i/o timing by default, the MT9M002 launches pixel da ta, frame_valid and line_valid with the rising edge of pixclk. the expectat ion is that the user captures d out [11:0], frame_valid and line_valid using the falling edge of pixclk. see figure 4 and table 2 on page 40 for i/o timing (ac) characteristics. figure 4: parallel i/o timing diagram note: pll disabled for t cp. c in _ si serial interface input pin capacitance C C C pf c load _ sd s data max load capacitance C C C 15 pf r sd s data pull-up resistor C C 1500 C table 1: two-wire serial bus characteristics (continued) symbol parameter condition min typ max unit extclk pixclk t r t f t extclk d out [11:0] frame_valid/ line_valid xxx xxx xxx xxx xxx xxx t pfl t pll t pd t pd t pfh t plh pxl_0 pxl_1 pxl_2 pxl_n 90% 10%
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 40 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor electrical specifications table 2: i/o timing characteristics notes: 1. extclk 16.5 mhz (min rise = 5ns, max rise = 6.3 ns) v pp = 2.3v midpoint 1.9v. 2. value equal to jitter on tester. 3. based on boards currently used for testing. symbol parameter condition min typ max unit f extclk input clock frequency pll disabled 8 C 16.5 mhz t extclk input clock period pll disabled 60.6 C 125 ns f pixclk output clock frequency pll enabled 8 C 99 mhz t pixclk output clock period pll enabled 10.10 C 125 ns t r 1 input clock rise time 54C99 mhz, pixclk, highClow voltage, midlevel condition 1C60ns t f 1 input clock fall time 1 C 60 ns t rp 1 pixclk rise time 2.4 C 3 ns t fp 1 pixclk fall time 2.2 C 3 ns extclk_dutycycle 40 50 60 % pixclk_duty cycle 99 mhz, midlevel condition (v dd , extclk duty cycle were varied) 40 50 60 % t (pix jitter) 2 jitter on pixclk high-low voltage, midlevel condition 0.5 0.7 1 ps t jitter 2 input clock jitter @ 8 mhz C C ps t jitter 2 input clock jitter @ 16.5 mhz CCps t cp extclk to pixclk propagation delay 54C99 mhz pixclk, highClow voltage, midlevel condition 12.6 14.4 16 ns f pixclk pixclk frequency 54 99 mhz t pd pixclk to data valid 0.6 1.5 2.3 ns t pfh pixclk to fv high 1.3 1.8 2.2 ns t plh pixclk to lv high 0.5 0.7 1.0 ns t pfl pixclk to fv low 1.4 2.1 2.6 ns t pll pixclk to lv low 0.5 0.7 1.0 ns c load 3 output load capacitance C 6.5 C pf c in 3 input pin capacitance C 2.5 C pf
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 41 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor dc electrical characteristics dc electrical characteristics the dc electrical characteristics are shown in table 3. table 3: dc electrical characteristics symbol parameter condition min typ max unit v dd core digital voltage 1.7 1.8 1.9 v v dd _io i/o digital voltage 2.6 2.8 3.1 v v aa analog voltage 2.6 2.8 3.1 v v aa _pix pixel supply voltage 2.6 2.8 3.1 v v dd _pll pll supply voltage 2.6 2.8 3.1 v v ih input high voltage v dd _io= 2.8v 2.0 C 3.3 v v il input low voltage v dd _io = 2.8v C0.3 C 0.8 v i in input leakage current no pull-up resistor; v in = v dd _io or d gnd 0.0176 0.5305 1.1425 a v oh output high voltage at specified i oh 2.17 2.68 3.05 v v ol output low voltage at specified i ol 0.2 0.28 0.39 v i oh output high current at specified v oh C0.014 C 0.014 ma i ol output low current at specified v ol 0.012 C 0.016 ma i oz tri-state output leakage current v in = v dd _io or gnd C 143 250 na i dd digital operating current streaming, full resolution 20 28.0 30 ma i dd _io i/o digital operating current streaming, full resolution 25 27.3 50 ma i aa analog operating current streaming, full resolution 60 65.0 100 ma i aa _pix pixel supply current streaming, full resolution 0 2.6705 4 ma i dd _pll pll supply current streaming, full resolution 1 3.0 5 ma i stby _a_off soft standby current C 0 0.48 1.6 ma i stby _a_on C 0 1.93 3.2 ma i stby _b_off C 0 6.53 8.8 ma i stby _b_on C 0 40.65 55.7 ma table 4: power consumption C parallel (at 30 fps, full resolution, 25c) symbol parameter typ current (ma) typ voltage (v) power parallel (mw) p vdd digital operating power 28.0 1.8 50.4 p vddio 1 i/o digital operating power 7.7 2.8 21.6 p vddio 2 (parallel) i/o power parallel 19.6 2.8 86.5 p vaa analog operating power 65.0 2.8 182.0 p vaapix pll supply power 5.6 2.8 15.7 p vddpll pll supply power 3.0 2.8 8.4 p total total power 364.6
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 42 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor dc electrical characteristics absolute maximum ratings caution stresses greater than those listed in table 5 may cause permanent damage to the device. expo- sure to absolute maximum rating conditions for extended periods may affect reliability. note: this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. table 5: absolute maximum values symbol parameter condition min max unit v dd _ max core digital voltage C0.3 1.9 v v dd _io_ max i/o digital voltage C0.3 3.1 v v aa _ max analog voltage C0.3 3.1 v v aa _pix_ max pixel supply voltage C0.3 3.1 v v dd _pll_ max pll supply voltage C0.3 3.1 v v in _ max input high voltage C0.3 v dd _io + 0.3 v i dd _ max digital operating current worst case current 28.3 ma i dd _io_ max i/o digital operating current worst case current 54.4 ma i aa _ max analog operating current worst case current 103 ma i aa _pix_ max pixel supply current worst case current 11.6 ma i dd _pll_ max pll supply current worst case current 7.3 ma i dd _lvds_max lvds operating current worst case current t op operating temperature measure at junction C30 70 c t stg storage temperature C40 85 c
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 43 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor package dimensions package dimensions the 48-pin clcc package mechanical drawing is shown in figure 5. figure 5: 48-pin clcc package outline note: all dimensions in millimeters. the 48-pin ilcc package mechanical drawing is shown in figure 6 on page 44. the optical center is aligned with package center as origin. seating plane 4.4 11.43 0.2 5.215 10.43 lid material: borosilicate glass 0.55 thickness wall material: alumina ceramic substrate material: alumina ceramic 8.8 4.4 10.43 4.72 5.215 0.8 typ 2 0.2 0.8 typ 8.8 48 1 10.9 0.1 ctr 47x 1 0.2 48x r0.15 48x 0.4 0.05 11.43 0.2 10.9 0.1 ctr 0.1 typ lead finish: au plating, 0.5 microns minimum thickness over ni plating, 1.27 microns minimum thickness 2.25 for reference only 1.7 for reference only 1.2 for reference only first clear pixel optical center and package center c a b optical area optical area: maximum rotation of optical area relative to package edges: 1o maximum tilt of optical area relative to seating plane a : 50 microns maximum tilt of optical area relative to top of cover glass d : 75 microns a d 1.35 0.15 0.9 0.075 0.8 for reference only 2.376 ctr 4x r0.15 ?0.20 a c b 3.168 ctr ?0.20 a b c image sensor die 0.1 a 0.05 4x 0.4
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 44 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor package dimensions figure 6: 48-pin ilcc package outline note: all dimensions in millimeters. 4.50 10.000 0.075 3.85 7.70 3.85 0.70 typ 0.70 typ 7.70 48 1 1.40 47x 0.80 48x 0.40 4.50 10.000 0.075 5.5 ctr 3.238 ctr 5.2 ctr 2.411 ctr c l c l lead finish: gold plating, 0.50 microns minimum thickness 4.20 c optical area maximum rotation of optical area relative to package edges b and c : 1o maximum tilt of optical area relative to seating plane a : 25 microns relative to top of cover glass d : 25 microns optical center = package center first clear pixel seating plane mold compound: epoxy novolac image sensor die lid material: borosilicate glass, 0.40 thickness 1.225 0.125 0.725 0.075 0.50 0.05 0.1 for reference only substrate material: plastic laminate a d b ?0.15 a b c ?0.15 a b c
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 45 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor revision history revision history rev. j. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/26/10 ? updated to non-confidential rev h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/4/10 ? restored correct figure 2: ?48-pin clcc 10 x 10 package pinout diagram (top view) ? parallel interface,? on page 9 (from rev. f) rev. g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2/8/2010 ? updated to aptina template ? moved register tables to MT9M002 register reference rev. f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7/22/2008 ? updated table 1, ?typical color sp ectral characteristics,? on page 36 ? updated table 1, ?key performance parameters,? on page 1 ? updated table 2, ?available part numbers,? on page 1 ? updated ?features? on page 1 ? updated figure 4: ?parallel i/o timing diagram,? on page 39 ? updated table 2, ?i/o timing characteristics,? on page 40 ? updated table 3, ?dc electrical characteristics,? on page 41 ? updated table 5, ?absolute maximum values,? on page 42 ? maximum extclk frequency updated to 16.5 mhz throughout the document ? added table 1, ?signal descriptions for MT9M002 in clcc package,? on page 8 ? figure 2: ?48-pin clcc 10 x 10 package pinout diagram (top view) ? parallel inter- face,? on page 9 ? table 2, ?signal descriptions for MT9M002 in ilcc package,? on page 10 ? added table 5, ?device addresses,? on page 19 ? updated ?pll setup sequence? on page 24 ? updated table 6, ?frequency parameters,? on page 24 ? updated ?exposure? on page 28 ? updated ?power-up sequence? on page 32 ? updated figure 2: ?chief ray angle (cra) vs. image height,? on page 37 ? updated table 1, ?two-wire serial bus characteristics,? on page 38 ? added figure 5: ?48-pin clcc package outline,? on page 43 rev. e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/07/2007 ? modified ?pll setup sequence? on page 24 ? modified ?reset? on page 34 ? updated qe curve figure 1: ?typical co lor spectral characteristics,? on page 36 ? changed registers from r0x06a throug h r0x06d, r0x080, and r0f8 to reserved ? changed r0x01e[14:13] to reserved ? changed r0x020[5:0] to reserved ? eliminated detailed descriptions of regist ers from r06a through r0x06d, r0x080, and r0f8 ? eliminated detailed descriptions of r0x01e[14:13] ? eliminated detailed descriptions of r0x020[5:0] ? eliminated detailed description of r0x094 ? updated ?standby and chip enable (power save mode)? on page 34
10 eunos road 8 13-40, singapore post center, singapore 408600 prodmktg@aptina.com www.aptina.com aptina, aptina imaging, digitalclarity, and the aptina logo are the property of aptina imaging corporation all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor revision history pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 46 ?2006 aptina imaging corporation all rights reserved. rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/23/2007 ? updated ?features? on page 1 high frame rate ? fixed default values in table 8, ?core register ? register list and default values,? on page 17 ? updated figure 2: ?power supply power-down sequence,? on page 33 and added notes rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 05/15/2007 ? updated table 1, ?signal descriptions for MT9M002 in clcc package,? on page 8 and table 2, ?signal descriptions for mt 9m002 in ilcc package,? on page 10. ? update figure 5: ?pixel array description,? on page 13. ? updated "row timing details" on page 17. ? updated table 8, ?core register ? register list and default values,? on page 17. ? updated table 9, ?core registers ? r egister description,? on page 22. ? updated "signal chain and datapath" on page 21. ? updated "readout modes" on page 27. ? updated "exposure" on page 28. ? updated "electronic rolling shutter" on page 28. ? updated "power-up sequence" on page 32. ? updated "power-down sequence" on page 33. ? added figure 1: ?power supply power-up sequence,? on page 32. ? added figure 2: ?power supply power-down sequence,? on page 33. ? updated figure 21: ?grr snapshot timing,? on page 31. ? updated "standby and chip enable (power save mode)" on page 34. ? updated table 2, ?i/o timing characteristics,? on page 40. rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12/06 ? updated table 1, ?key performance parameters,? on page 1. ? updated table 2, ?available part numbers,? on page 1. ? updated table 1, ?signal descriptions for MT9M002 in clcc package,? on page 8 and table 2, ?signal descriptions for mt 9m002 in ilcc package,? on page 10. ? removed packaging options section and table 4. ? update figure 1: ?block diagram ? parallel output,? on page 6. ? update figure 4: ?typical configuration ? parallel connection,? on page 12. ? updated "two-wire serial interface sample write and read sequences" on page 20. ? updated ?power-up sequence? on page 32. ? updated ?power-down sequence? on page 33. ? updated ?hard reset? on page 34. ? updated ?soft reset? on page 34. ? updated table 2, ?i/o timing characteristics,? on page 40. ? update table 4, ?power consumption ? parallel,? on page 41. ? updated table 5, ?absolute maximum values,? on page 42.
pdf: 9596719696/source: 3435392951 aptina reserves the right to change products or specifications without notice. MT9M002_ds - rev. j pub. 5/10 en 47 ?2006 aptina imaging corporation. all rights reserved. MT9M002: 1/4.5-inch 1.6mp cmos digital image sensor revision history rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/06 ?initial release

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